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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
DEFLECTION PROCESSOR
32-SDIP-400
The S1D2511B01 is a monolithc integrated circuit assembled in 32 pins shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multifrequency computer display monitors. The internal sync processor, combined with the very powerful geometry correction block make the S1D2511B suitable for very high performance monitors with very few external components. The horizontal jitter level is very low. It is particularly well suited for high-end 15" and 17" monitors.
FUNCTIONS
* Defiection Processor * I2C BUS Control * B+ Regulator * Vertical Parabola Generator * Horizontal and Vertical dynamic focus
ORDERING INFORMATION
Device S1D2511B01-A0B0 Package 32-SDIP Operating Temperature 0 C -- 70 C
FEATURES
(HORIZONTAL) * Self-adaptative * Dual PLL concept * 150kHz maximum frequency * X-RAY protection input * I2C controls : Horizontal duty-cycle, H-position,free running frequency, frequency generator for burn-in mode. (VERTICAL) * Vertical ramp generator * 50 to 165Hz AGC loop * Geometry tracking with V-POS & AMP * I2C Controls : V-AMP, V-POS, S-CORR, C-CORR (I2C GEOMETRY CORRECTIONS) * Vertical parabola generator (Pincushion-E/W, Keystone) (GENERAL) * Sync Processor * 12V supply voltage * Hor. & Vert, lock/unlock outputs * Read/Write I2C interface * Vertical moire * B+ Regulator -Internal PWM generator for B+ current mode step-up converter. - Switchable to step-down converter - I2C adjustable B+ reference voltage - Output pulses synchronized on horizontal frequency - Internal maximum current limitation. * Horizontal Dynamic Phase (Side Pin balance & parallelogram) * Horizontal and vertical dynamic focus (Horizontal Focus Amplitude, Horizontal Focus Symmetry, Vertical Focus Amplitude)
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
BLOCK DIAGRAM
H POSITION
HLOCKOUT
PLL1F
PLL2C
R0
7 13
8
3
6
C0
5
12
HFLY
4
HREF
VREF
HGND
11
PHASE/ FREQUENCY COMPARATOR H-PHASE(7 bits)
VCO
PHASE COMPARATOR
PHASE SHIFTER
H-DUTY (5 bits)
HOUT BUFFER
LOCK/UNLOCK IDENTIFICATION
Forced Freq. 2 bits Free running 5 bits
HOUT 26
SAFETY PROCESSOR
Vcc XRAY B+ ADJUST 7 bits B+ CONTROLLER
14 28 15 16 17 9
Amp & symmetry 2x5 bits X
COMP B+ OUT REGIN ISENSE BGND HFOCUS CAP
H/HVIN VSYNC IN VCC XRAY VREF VGND
1 2
SYNC INPUT SELECT (1bit)
SYNC PROCESSOR +
X
2
Spin Bal 6 bits
2
29 25 21 19
6 bits 8 bits VREF
VSYNC
X
Key Bal 6 bits
2
MOIRE CANCEL 5 BITS+ON/OFF GEOMETRY TRACKING
+ VAMP 6 bits
10
FOCUS
5V SDA SCL GND
32 31 30 27
RESET GENERATOR S AND C CORRECTION I 2 C INTERFACE VERTICAL OSCILLATOR RAMP GENERATOR
VAMP 7 bits X keyst 6 bits
2
PCC 7 bits
+ X
+ VPOS 7bits
22 VCAP
20 VACCAP
18 BREATH
23 VOUT
24 EWOUT
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
PIN CONFIGURATIONS
1 2
H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F
5V SDA
32 31
3 4 5 6 7
SCL VCC BOUT GND
30 29 28 27 26
S1D2511B
HOUT
8 9 10 11 12
HPOSITION HFOCUSCAP FOCUSOUT
XRAY EWOUT VOUT
25 24 23 22 21
HGND HFLY
VCAP VREF
13 14 15 16
HREF COMP REGIN
VAGCCAP VGND BREATH
20 19 18 17
ISENSE
B+GND
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PIN DESCRIPTION
Table 1. Pin Description
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HFOCUSCAP FOCUSOUT HGND HFLY HREF COMP REGIN ISENSE B+GND BREATH VGND VAGCCAP VREF VCAP VOUT EWOUT XRAY HOUT GND BOUT Vcc SCL SDA 5V Description TTL compatible horizontal sync input(Separate or composite) TTL compatible vertical sync input (for separated H&V) First PLL lock/unlock output (0V unlocked - 5V locked) Second PLL loop filter Horizontal oscillator capacitor Horizontal oscillator resistor First PLL loop filter Horizontal position filter(Capacitor to be connected to HGND) Horizontal dynamic focus oscillator capacitor Mixed horizontal and vertical dynamic focus output Horizontal Section Ground Horizontal Flyback Input (positive polarity) Horizontal Section Reference Voltage (to be filtered) B+ error amplifier output for frequency compensation and gain setting Regulation input of B+ control loop Sensing of external B+ switching transistor current or switch for step-down converter Ground (related to B+ reference adjustment) DC breathing input control(Compensation of vertical amplitude against EHV variation) Vertical section ground Memory capacitor for automatic gain control loop in vertical ramp generator Vertical section reference voltage (to be filtered) Vertical sawtooth generator capacitor Vertical ramp output (with frequency independant amplitude and S or C corrections if any). It is mixed with vertical position voltage and vertical moire. Pincushion-East/West correction parabola output X-RAY protection input (with internal latch function) Horizontal drive output (internal transistor, open collector) General ground (referenced to Vcc) B+ PWM regulator output Supply voltage (12V typ) I2C clock input I2C data input Supply voltage (5V typ)
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
REFERENCE DATA
Table 2. Reference Data Parameter Horizontal frequency Autosynch frequency (for given R0 and C0) Horizontal sync polarity input Polarity detection (on both horizontal and vertical section) TTL Composite synch Lock/Unlock identification (on both horizontal 1st PLL and vertical section) I2C control for H-Position XRay protection I2C horizontal duty cycle adjust I2C free running frequency adjustment Stand-by function Dual polarity H-Drive outputs Supply voltage monitoring PLL1 inhibition possibility Blanking output Vertical frequency Vertical autosync (for 150nF on Pin22 and 470nF on Pin20) Vertical S-Correction Vertical C-Correction Vertical amplitude adjustment DC breathing control on Vertical amplitude East/West parabola output(also known as Pin cushion output) East/West correction amplitude adjustment Keystone adjustment Internal dynamic horizontal phase control Side pin balance amplitude adjustment Parallelogram adjustment Tracking of geometric corrections with vertical amplitude and position Value 15 to 150 1 to 4.5FO YES YES YES YES 10 YES 30 to 60 0.8 to 1.3FO YES NO YES NO NO 35 to 200 50 to 165 YES YES YES YES YES YES YES YES YES YES YES Hz Hz % FH % Unit kHz FH
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 2. Reference Data (Continued) Parameter Reference voltage (both on horizontal and vertical) Dynamic focus (both on horizontal and vertical) I2C horizontal dynamic focus amplitude adjustment I2C horizontal dynamic focus symmetry adjustment I2C vertical dynamic focus amplitude adjustment Deflection of input Sync type(biased from 5V alone) Vertical moire output I2C controlled V-moire amplitude Frequency generator for burn-in Fast I2C read/write B+ regulation adjustable by I2C Value YES YES YES YES YES YES YES YES YES 400 YES kHz Unit
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
ABSOLUTE MAXIMUM RATINGS
No 1 2 3 Item Supply voltage (pin 29) Supply voltage (pin 32) Maximum voltage on Pin 4 Pin 9 Pin 5 Pins 6,7,8,14,15,16,20,22 Pins 10,18,23,24,25,26,28 Pins 1,2,3,30,31 ESD susceptibillty Human body model, 100pF discharge through 1.5K EIAJ norm, 200pF discharge through 0 Storage temperature Operating temperature Symbol VCC VDD VIN Value 13.5 5.7 4.0 5.5 6.4 8.0 VCC VDD 2 300 Tstg Topr - 40, +150 0, +70 Unit V V V V V
4
VESD
kV V C C
5 6
THERMAL CHARACTERISTICS
No 1 2 Junction temperature Junction-ambient thermal resistance Item Symbol Tj ja Value +150 65 Unit C C/W
SYNC PROCESSOR
OPERATING CODNITIONS Table 3. Sync Processor Operating Codnitions Parameter Horizontal sync input voltage Minimum horizontal input pulse duration Maximum horizontal input signal duty cycle Vertical sync input voltage Minimum vertical sync pulse width Maximum vertical sync input duty cycle Maximum vertical sync width on TTL H/V composite Sink and source current Symbol HsVR MinD Mduty VsVR VSW VSmD VextM IHLOCKOUT Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 Pin 3 0 5 15 750 250 Min 0 0.7 25 5 Typ Max 5 Unit V s % V s % s A
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S1D2511B01
ELECTRICAL CHARACTERISTICS (V = 5V, Tamb = 25 Table 4. Sync Processor Electrical Characteristics Symbol Horizontal and vertical input threshold voltage (pin 1, 2) Horizontal and vertical pull-up resister Falling and rising output CMOS buffer RIN TfrOut VHlock
LOCKOUT=
Conditions Low level High level
Typ
Max 0.8 V K 200 ns V V %
200
(pin 3)
Unlocked, I
-250 A = +250
0 5 35
TH(9)
VoutT
C0 = 820pF
I2
(See also I2
2
C sub address control)
2
C Read/Write Operating Conditions Symbol VinH VinL fSCL tBUF tHDS tSUP tLOW tHIGH tHDAT tSUPDAT tR tF Min 3.0 0 1.3 0.6 0.6 1.3 0.6 0.3 0.25 Max 5.0 1.5 200 1.0 3.0 Unit V V kHz uS uS uS uS uS uS uS uS uS
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
I2C BUS Timing Requirement
Stop:Clock High Start:Clock High
tBUF
tHDAT
SDA tHDS SCL tLOW Data Change:Clock Low tHIGH tSUPDAT tSUP
ELECTRICAL CHARACTERISTICS ( VDD = 5V, Tamb = 25 C) Table 6. I 2C Read/Write Electrical Characteristics Parameter I2C PROCESSOR Maximum clock frequency Low period of the SCL clock High period of the SCL clock SDA and SCL input threshold Acknowledge output voltage on SDA input with 3mA Fscl Tlow Thigh Vinth VACK Pin 30 Pin 30 Pin 30 Pin 30, 31 Pin 31 1.3 0.6 2.2 0.4 400 kHz s s V V Symbol Conditions Min Typ Max Unit
HORIZONTAL SECTION
OPERATING CONDITIONS Table 7. Horizontal Section Operating Conditions Parameter VCO
Minimum oscillator resistor Minimum oscillator capacitor Maximum oscillator frequency R0(Min.) C0(Min.) F(Max.) Pin 6 Pin 5 6 390 150 K pF kHz
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT SECTION
Maximum input peak current Horizontal drive output maximum current I12m HOI Pin 12 Pin26, sunk current 5 30 mA mA
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
ELECTRICAL CHARACTERISTICS ( VDD = 5V, Tamb = 25 C) Table 8. Horizontal Section Electrical Characteristics Parameter SUPPLY AND REFERENCE VOLTAGE
Supply voltage Supply voltage Supply current Supply current Horizontal reference voltage Vertical reference voltage Max. sourced current on VREF-H Max. sourced current on VREF-V Vcc VDD ICC IDD VREF-H VREF-V IREF-H IREF-V Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I=-2mA Pin 21, I=-2mA Pin 13 Pin 21 7.4 7.4 10.8 4.5 12 5 50 5 8 8 8.6 8.6 5 5 13.2 5.5 V V mA mA V V mA mA
Symbol
Conditions
Min
Typ
Max
Unit
1st PLL SECTION
Polarity integration delay VCO control voltage (pin 7) HpoIT VVCO Pin 1 VREF-H=8V f0 fH (Max.) R0=6.49K, C0=820pF, dF/dV=1/11R0C 0 % of horizontal period Sub-address 01 Byte x 1111111 Byte x 1000000 Byte x 0000000 PLL1 is unlocked PLL1 is locked R0=6.49K,C0=820pF, f0=0.97/8R0C0 0.75 1.3 6.2 17 10 2.6 3.2 3.8 140 1 140 1 -150 Sub-address 02 Byte x x x 11111 Byte x x x 00000 R0=6.49K,C0=820pF, from f0+0.5KHz to 4.5Fo fH(Min.) fH(Max.) Sub-address 02 2F0 3F0 ms V V kHz/V % V V V A mA A mA ppm/c
VCO gain (pin 7 ) Horizontal phase adjustment(11) Horizontal phase setting value(Pin 8)(11) Minimum current value Typical value Maximum value PLL1 filter current charge Free running frequency Free running frequency thermal drift (no drift on external components)(7) Free running frequency adjustment Minimum value Maximum value PLL1 capture range
VCOG Hph Hphmin Hphtyp Hphmax IPII1U IPII1L fo dF0/dT
f0(Min.) f0(Max.) CR
0.8 1.3
F0 F0
23.5 100
KHz KHz
Safe forced frequency SF1 Byte 11 x x x x x x SF2 Byte 10 x x x x x x
SFF
2ND PLL SECTION HORIZONTAL OUTPUT SECTION
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Table 8. Horizontal Section Electrical Characteristics (Continued) Parameter
Flyback input threshold voltage (pin12) Horizontal jitter Horizontal drive output duty-cycle (pin 26) (1, 2) Low level High level X-RAY protection input threshold voltage Internal clamping levels on 2nd PLL loop filter (pin 4 ) Threshold voltage to stop H-out, V-out when VCC < VSCinh Horizontal drive output (low level) HDmin HDmax XRAYth Vphi2 VSCinh HDvd
Symbol
FBth Hjit
Conditions
Min
0.65
Typ
0.75 70
Max
Unit
V ppm
Sub-address 00 Byte xxx11111 Byte xxx00000 Pin 25(12) Low level High level Pin 29 Pin 26 IOUT=30mA
(2)
30 60 8 1.6 3.7 7.5 0.4
% % V V V V V
HORIZONTAL DYNAMIC FOCUS FUNCTION
Horizontal dynamic focus sawtooth Minimum level Maximum level Horizontal dynamic focus sawtooth Discharge width Bottom DC output level DC output voltage thermal drift Horizontal dynamic focus amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 Horizontal dynamic focus keystone Min A/B Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 HDFst Capacitor on HfocusCap and C0=820pF, TH=20S, Pin 9 Start by Hfly center RLOAD=10K, pin 10 Sub-address 03, pin 10, FH=50kHz, Keystone Typ Sub-address 04, FH = 50kHz, Typ amp B/A A/B A/B 2 4.7 400 2 200 1 1.5 3 V V ns V ppm/C Vpp Vpp Vpp
HDFdis HDFDC TDHDF HDFamp
HDFkeyst
2.2 2.2
3.5 1.0 3.5
VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA)
Vertical dynamic focus parabola (added to horizontal one) amplitude with VOUT and VPOS typical Min. Byte 000000 Typ. Byte 100000 Max. Byte 111111 Parabola amplitude function of VAMP (tracking between VAMP and VDF) with VPOS typ. (see figure 1)
(3)
AMPVDF
Sub-address 0F
0 0.5 1 VDFAMP Sub-address 05 Byte 10000000 Byte 11000000 Byte 11111111 Sub-address 06 Byte x0000000 Byte x1111111 0.6 1 1.5 0.52 0.52
Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp
Parabola assymetry function of VPOS control (tracking between VPOS and VDF) with VAMP Max.
VHDFKeyt
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
VERTICAL SECTION
OPERATING CONDITIONS Table 9. Vertical Section Operating Conditions Parameter OUTPUTS SECTION
Maximum EW output voltage Minimum EW output voltage Minimum load for less than 1% vertical amplitude drift VEWM VEWm RLOAD Pin 24 Pin 24 Pin 20 1.8 65 6.5 V V M
Symbol
Conditions
Min
Typ
Max
Unit
ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 C) Table 10. Vertical Section Electrical Characteristics Parameter VERTICAL RAMP SECTION
Voltage at ramp bottom point Voltage at ramp top point (with sync) VREF-V Voltage at ramp top point (without sync) Vertical sawtooth discharge time duration (pin 22) Vertical free running frequency see
(4, 5)
Symbol
Conditions
Min
Typ
Max
Unit
VRB VRT VRTF VSTD VFRF
VREF-V=8V, pin 22 VREF-V=8V, Pin 22 Pin 22 With 150nF cap COSC(pin22)=150nF measured on pin 22 C22=150nF 5% See
(6)
2 5
VRT-01
V V V s Hz
70 100
AUTO -SYNC frequency(13) Ramp amplitude drift versus frequency at Maximum vertical amplitude Ramp linearity on pin 22 (I22/I22) see (4, 5)
ASFR
50
165
Hz
RAFD RIin
C22=150nF
50Hz200 0.5
TBD
ppm/ Hz %
V20=4.3v, 2.5Vertical position adjustment voltage (pin 23 - VOUT centering)
Vpos
3.65
3.2 3.5 3.8 2.25 3 3.75 5
3.3
V V V V V V mA % %
Vertical output voltage (peak-to-peak on pin 23 )
VOR
2.5
3.5
Vertical output Maximum current(Pin 23) Max vertical S-correction amplitude(14) XOXXXXXX inhibits S-CORR X1111111 gives max S-CORR
VOI dVS Sub address 07
V/Vpp at TV/4 V/Vpp at 3TV/4
-4 +4
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Table 10. Vertical Section Electrical Characteristics (Continued) Parameter
Vertical C-Corr amplitude XOXXXXXX inhibits C-corr
Symbol
Ccorr
Conditions
Sub address 08 Byte X1000000 Byte X1100000 Byte X1111111
Min
Typ
Max
Unit
V/Vpp at TV/2
-3 0 3 % % %
EAST/WEST FUNCTION
DC output voltage with typ Vpos, keystone, corner and corner balance inhibited DC output voltage thermal drift Parabola amplitude with Vamp Max. V-Pos typ, keystone ilhibited EW DC TDEW DC EWpara pin 24, see figure 2 see note 7 Sub address 0A Byte 1111111 Byte 1010000 Byte 1000000 Sub address 05 Byte 1000000 Byte 1100000 Byte 1111111 Sub address 09 2.5 100 V ppm/ C V V V V V V
2.5 1.25 0 0.45 0.8 1.25
Parabola amplitude function of V-AMP control (tracking between V-AMP and E/W) with typ Vpos ketstone, EW Typ amplitude (8)
EWtrack
Keystone adjustment capability with typ Vpos, EW typ amplitude and vertical amplitude max,
(8)
KeyAdj
A/B Ratio(see figure 2) B/A Ratio
Intrinsic keystone function of V-POS control (tracking between V-pos and EW) Max amplitude and vertical amplitude max. (10) A/B Ratio B/A Ratio KeyTrack
Byte 1x000000 Byte 1x111111 Sub address 09
1 1
Vpp Vpp
Byte x0000000 Byte x1111111
0.52 0.52
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION
Side pin balance parabola amplitude (figure3) with Vamp max, V-POS typ and parallelogram inhibited
(8,9)
SPBpara
Sub address 0D Byte x1111111 Byte x0000000 Sub address 05 Byte 10000000 Byte 11000000 Byte 11111111 Sub address 0E Byte x1111111 Byte x1000000
+1.4 -1.4
0.5 0.9 1.4
%TH %TH %TH %TH %TH
Side pin balance parabola amplitude function of Vamp control (tracking between Vamp and SPB) with SPB max, V-POS typ and parallelogram inhibited(8,9) Parallelogram adjustment capability with Vamp max, V-POS typ and SPB max A/B Ratio B/A Ratio
(8,9)
SPBtrack
ParAdj
+1.4 -1.4
%TH %TH
Intrinsic parallelogram function of Vpos control (tracking between V-pos and DHPC) with Vamp max, SPB max and parallelogram inhibited(8, 9) A/B Ratio B/A Ratio
Partrack
Sub address 06
Byte x0000000 Byte x1111111
0.52 0.52
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Table 10. Vertical Section Electrical Characteristics (Continued) Parameter VERTICAL MOIRE
Vertical moire (measured on VOUTDC) pin 23 VMOIRE Sub address 0C Byte 01x11111 6 mV
Symbol
Conditions
Min
Typ
Max
Unit
BREATHING COMPENSATION
DC breathing control range(15) Vertical output variation versus DC breathing control (Pin 23) BRRANG BRADj V18 V18VREF-V V18=4V 1 0 -10 12 V % %
B+ SECTION
OPERATING CONDITIONS Table 11. B+ Section Operating Conditions Parameter
Minimum feedback resistor
Symbol
FeedRes
Conditions
Resistor between pins 15 and 14
Min
5
Typ
Max
Unit
K
ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamp = 25 C ) Table 12. B+ Section Electrical Characteristics Parameter
Error amplifier open loop gain Unity gain band width Regulation input bias current Maximum guaranted error amplifier output current Current sense input voltage gain Max current sense input thres hold voltage Current sense input bias current Maxmum external power transistor on time B+ output low level saturation voltage Internal reference voltage
Symbol
OLG UGBW IRI EAOI CSG MCEth ISI Tonmax
Conditions
At low frequency (10) see (7) Current sourced by pin 15 (PNP base) Current sourced by pin 14 Current sunk by pin 14 Pin 16 Pin 16 Current sunk by pin 16 (NPN base ) % of H-period @ f0=27kHz
(16)
Min
Typ
85 6 0.2
Max
Unit
dB MHz A
0.5 2 3 1.2 1 100
mA mA
V A %
B+OSV IVREF
V28 with I28=10mA On error amp (+) input for subaddress 0B byte 1000000
0.25 4.8
V V
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Table 12. B+ Section Electrical Characteristics
Internal reference voltage adjustment range Threshold for step-up/step-down selection Falling time VREFADJ DWMSEL tFB+ Byte 111111 Byte 000000 Pin 16 Pin 28 +20 -20 6 100 % % V ns
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
NOTES;
1.Duty cycle is the ratio of power transistor OFF time period. Power transistor is OFF when output transistor is OFF. 2.Initial condition for safe operation start up. 3.S and C correction are inhibited so the output sawtooth has a linear shape. 4.With register 07 at byte x0xxxxxx (s-correction control is inhibited) then the S correction is inhibited, consequently the sawtooth has a linear shape. 5.With register 08 at byte x0xxxxxx (C-Correction control is inhibited) then the C correction is inhibited, consequently the sawtooth has a linear shape. 6.It is frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin 22, and with a constant ramp amplitude. 7.These parameters are not tested on each unit. They are measured during out internal qualification. 8.Refers to notes 4 & 5 from last section. 9.TH is the Horizontal period. 10.These parameters are not tested on each unit. They are measured during our internal qualification procedure which incudes characterization on batches comming from corners of our processes and also temperature char acterization. 11. See Figure 11 for explanation of reference phase. 12. See Figure 15. 13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on Pin 22 and with a constant ramp amplitude. 14. TV is the vertical period. 15. When not used the DC breathing control pin must be connected to 12V. 16. The external power transistor is OFF during 400ns of the HFOCUSCAP discharge.
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
VDFDC
VDFAMP B
A
Figure 1. Vertical Dynamic Focus Function
EWPARA B
A
EWDC
Figure 2. E/W Output
EWPARA B
A
SPBPARA DHPCPC
Figure 3. Dynamic Horizontal Phase Control Output
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Function
Sub address
Pin
Byte
Specification VOUTDC 2.25V VOUTDC 3.75V
Picture Image
10000000 Vertical Size 05 23 11111111
Vertical Position DC Control
06
23
x0000000 x1000000 x1111111
3.2V 3.5V 3.8V
Vertical S Linearity
x0xxxxxx Inhibited 07 23 x1111111 Vpp
V V =4% Vpp V Vpp V =3% Vpp V Vpp
x1000000 Vertical C Linearity
08
23
x1111111
V =3% Vpp
Figure 4. Typical Vertical Output Waveforms
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Function
Sub address
Pin
Byte EWamp Typ.
Specification
Picture Image
Key Stone (Trapezoid) Control
10000000 09 24
1.0V
2.5V
1.0V
2.5V
1111111
Keystone Inhibited E/W (Pin Cushion) Control 0A 24 1x000000
2.5V
0V
1x111111
2.5V
SPB Inhibited 3.7V Parallelogram Control 0E Internal x1000000 3.7V x111111 Parallelogram Inhibited Side Pin Balance Control 0D Internal 3.7V x0000000 x1111111 3.7V 1.4% TH 1.4% TH 1.4% TH 1.4% TH
Vertical Dynamic Focus with Horizontal
32 2V Figure 5. Geometry Output Waveforms
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S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C BUS ADDRESS TABLE
Slave Address (8C): Write Mode Sub Address Definition D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal drive selection/horizontal duty cycle Horizontal position Forced frequcny /free running frequency Synchro priority / horizontal focus amplitude Refresh /horizontal focus keystone Vertical ramp amplitude Vertical position adjustment S Correction C Correction E/W keystone E/W amplitude B+ reference adjustment Vertical moire Side pin balance Parallelogram Vertical dynamic focus amplitude
Slave Address (8D): Read Mode No Sub Address needed
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
I2C BUS ADDRESS TABLE (continued)
D8 D7 HDrive 0, off [1],on Xray 1,reset [0] 1,on, [0],off Sync 0, comp [1], sep Detect refresh [0], off Vramp 0, off [1], on D6 D5 WRITE MODE Horizontal duty cycle [0] [0] [0] [0] [0] 00 D4 D3 D2 D1
Horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0]
01
Forced frequency 02 1,F0x2 [0],F0x3 [0]
Free running frequency [0] [0] [0] [0]
Horizontal focus amplitude [1] [0] [0] [0] [0]
03
Horizontal focus keystone [1] [0] [0] [0] [0]
04
Vertical ramp amplitude adjustment [1] [0] [0] [0] [0] [0] [0]
05
06 S Select 1, on [0] C Select 1, on [0] EW key 0, off [1] EW sel 0, off [1] Test H 1, on [0], off Test V 1, on [0], off SPB sel 0, off [1] Parallelo 0, off [1]
Vertical position adjustment [1] [0] [0] [0] S Correction [1] [0] [0] C Correction [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]
07
08
East/West keystone [1] [0] [0] East/West amplitude [1] [0] [0] [0] [0] [0] [0] [0] [0] [0]
09
0A
B+ reference adjustment [1] Moire 1, on [0] [0] [0] [0] [0] Vertical Moire [0] [0] [0] [0] [0] [0] [0]
0B
0C
Side pin balance [1] [0] [0] Parallelogrm [1] [0] [0] [0] [0] [0] [0] [0] [0]
0D
0E
0F
Vertical dynamic focus amplitude [1] [0] [0] [0] [0] [0]
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
READ MODE 00 Hlock 0, on [1], no Vlock 0, on [1], no Xray 1,on [0],off Polarity detection H/V pol [1],negative V pol [1], negative Synchro detection Vext det [0],no det H/V det [0],no det V det [0], nodet
[ ] initlal value
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS Power Supply The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Perfect operation is obtained if Vcc and VDD are maintened in the limits: 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during transient phase of Vcc switching on, or switching off, the value of Vcc is monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V typically. In the same manner, VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C control table for power on reset). In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage references (the unigue typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and on one for the horizontal one. If needed, these voltage references can be used (until Iload is less than 5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. I2C Control KB2511 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated control pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and a data input. The general function and the bus protocol are specified in the philips-bus data sheets. The interface (data and clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes of up to 500ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress. It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+ reference adjustment. 17 bits are also dedicated to several controls (ON/OFF, horizontal forced frequency, sync priority, detection refresh and Xray reset).
22
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Read Mode During read mode the second byte transmits the reply information. The reply byte contains horizontal and vertical lock/unlock status, Xray activated or not, the horizontal and vertical polarity detection. It also contains synchro detection status that is useful for P to assign sync priority. A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and SCL) to high impedance. See I2C subaddress and control tables. Sync processor The internal sync processor allows the S1D2511B01 to accept any kind of input synchro signals: - separated horizontal & vertical TTL-compatible sync signals, - composite horizontal & vertical TTL-compatible sync signals. Sync identification Status The MCU can read (address read mode : 8D) the status register via the I2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and(when 12V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5V is supplied. In order to choose the right sync priority the MCU may proceed as follows(see I2C Address Table): - refresh the status register, - wait at least for 20ms(MAX. vertical period), - read this status register, Sync priotity choice should be: Vext det No Yes H/V det Yes Yes V det Yes No Sync priority subaddress 03 (D8) 1 0 Comment sync type Separated H & V Composite TTL H & V
Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present and that no sync change occured. Sync processor is also giving sync polarity information. IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the Xary protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or directly resetting it via the I2C interface. Sync Inputs Both H/HVin and Vsyncin inputs are TTL compatible trigger with hysterisis to avoid erratic detection. Both inputs include a pull up register connected to VDD. Sync Processor Output The sync processr indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync. HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of the status regiser is set to 0. This information is mainly used to trigger safety procedures(like reducing B+ value) as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure for
23
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
free running frequency(fo) adjustment. Sending the desired fo on the sync input and progressively decreasing the free running frequently I2C register value(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running frequency this way allows to fully exploit the S1D2511B01 horizontal frequency range. HORIZONTAL PART Internal input conditions Horizontal part is internally fed by synchro processor with a digital signal corresponding to horizontal synchro pulses or to TTL composite input. concerning the duty cycle of the input signal, the following signals (positive or negative)may be applied to the circuit. Using internal integration, both signals are recognized on condition that Z/T < 25%, synchronisation occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s.
Z T
Z
Figure 6. An other integration is able to extract vertical pulse of composite synchro if duty cycle is more than 25% (typically d = 35%) (7) c
TRAMEXT
d Figure 7.
d
The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input which is intolerent to wrong or missing pulse. PLL1 The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO). The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and sourced (I = 1mA typ. when locked, I = 140mA when unlocked). This difference between lock/unlock permits a smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked avoiding horizontal too fast frequency change. The dynamic bahaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A CRC filter is generally used (see figure 8 )
24
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
PLL1F 7
1.8K 4.7uF 1uF
Figure 8. PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump and the filter (see figure 9 ). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.
H-LOCKCAP 8 LOCKDET
PLL1F R0 LOCK/UNLOCK STATUS 7 8
C0 9
I2C SMFE TRAMEXT MODE High
HSYNC
INPUT INTERFACE
TRAMEXT
COMP1
E2 Low
CHARGE PUMP
PHASE ADJUST
PLL INHIBITION
VCO
I2C OSC HPOS Adj.
Figure 9. Block Diagram
25
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
I2C Free running Adjustment Loop Filter 7
a ID
ID 2
+ 6.4V
-
+
RS FLIP FLOP
+ -
1.6V
4 I0 2
-
(0.80(1.3V < V7 < 6V)
6 R0
5
6.4V
Co
1.6V
0 0.84T T
Figure 10. Details of VCO The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 10). The theorical frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible to adjust free running frequency through I2C. This adjustment can be made automatically on the manufacturing line without manual operation by using hlock/unlodk information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is the free running frequency at power on reset). The sync frequency has to be always higher than the free running frequency. As an example for a synchro range from 24kHz to 100kHz, the suggested free running frequency is 23kHz. An other feature is the capability for MCU to force horizontal frequency throw I2C to 2xF0 or 3xF0 (for burn in mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is forced to 2.66V for 2xF0 or 4.0V for 3xF0. The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparism between the sawtooth of the VCO and an internal DC voltage I2C adjustable between 2.65V and 3.75V (corresponding to 10%) (see figure 11)
H Osc Sawtooth
7/8TH
1/8T H 6.4V 2.65V < Vb < 3.75V Vb
Phase REF1 H Synchro
1.6V
Phase REF1 is obtained by comparision between the sawtooth and a DC voltage adjustable between 2.6V and 3.8V. The PLL1 ensures the exact coindidence between the signals phase REF and HSYNS. A TH/10 phase adjustment is possible
Figure 11. PLL1 Timing Diagram
26
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
The S1D2511B01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync processor). The block function is described in figure 12. When PLL1 is unlocked, It forces Hlockout to leave high. The lock/unlock information is also available throw I2C read. PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparism with the sawtooth of the VCO (figure 12). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump(typical output current:0.5mA). The flyback input is composed of an NPN transistor. This input must be current driven. The maximum recommanded input current is 5mA (see figure 13). The dury cycle is adjustable through I2C from 30% to 60%. For startup safe operation, initial duty cycle (after power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor. The maximum storage time(Ts MAX.) is (0.38TH-TFLY/2). Typically, TFLY/TH is around 20% which means that Ts max is around 28% of TH. H Osc Sawtooth
7/8TH
1/8T H 6.4V 3.7V 1.6V
Flyback Internally Shaped Flyback H drive Ts Duty Cycle Figure 12. PLL2 Timing Diagram
400 HFLY 12 20K Q1
GND 0V Figure 13. Flyback Input Electrical Diagram
27
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
Output Section The H-drive signal is transmitted to the output through a shaping block ensuring TS and I2C adjustable duty cycle. In order to secure scanning power part operation, the output is inhibited in the following circumstances: - Vcc too low - Xray protection activated - During horizontal flyback - H Drive I2C bit control is off. The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see figure 14).
26 H-DRIVE
Figure 14. The output NPN is in off-state when the power scanning transistor is also in off-state. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. X-RAY protection The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It inhibits the H-Drive and B+ outputs. This protection is latched; It may be reset either by Vcc switch off or by I2C(see figure 15). Horizontal and vertical dynamic focus The S1D2511B01 delivers and horizontal parabola added on a vertical parabola wavefrom on pin 10. This horizontal parabola is performed from a sawtooth in phase with flyback pulse middle. This sawtooth is present on pin 9 where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically). Symmetry (keystone) and amplitude are I2C adjustable (see figure 16). Vertical dynamic focus is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal has to be connected to the CRT focusing grids.
28
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
Vcc checking Vcc VSCinh
I2C Drive on/off HORIZONTAL OUTPUT INHIBITION I2C ramp on/off VERTICAL OUTPUT INHIBITION
+
XRAY protection Xray S Q Vcc off or I2C reset R Horizontal flyback 0.7V
+
BOUT
Figure 15. Safety Functions Block Diagram
Horizontal flyback Internal triggerd Horizontal flyback Horizontal focus Cap Sawtooth Horizontal dynamic focus parabola output
4.7V 2V 400ns 2V Moire output Figure 16.
29
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
VERTICAL PART Geometric Corrections The principle is represented in figure 17. Parabola Generator VDCMID(3.5V)
23
V.Focus AMP I
Horizontal Dynamic Focus
+ 2
10
Dynamic focus
EW amp + VDCMID (3.5V)
keystone
24
EW output
Vertical Ramp VOUT
sidepin amp
VDCMID (3.5V)
+ phase
To horizontal
Parallelogram
Sidepin balance output current
Figure 17. Geometric Correcitions Principle Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal phase control correction, and vertical dynamic focus correction. The base of the parabola generator is an analog multiplier, the output current of which is equal to: I = k* ( VOUT - VDCMID ) 2 Where Vout is the vertical output ramp(typically between 2 and 5V) and VDCMID is 3.5V(for VREF-V=8V). The VOUT sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by 0.3V. In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry tracking. Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum vertical amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages saturation. This must be avoided by limiting the output voltage by appropriate I2C registers values. For E/W part and Dynamic Horizontal phase control part, a sawtooth shaped differential current in the following form is generated: I' = k' * ( VOUT - VDCMID ) 2 Then I and I'are added together and converted into voltage for the E/W part. Each of the two E/W components or the two Dynamic horizontal phase control ones may be inhibited by their own I2C select bit. The E/W parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external resistor (10K). It can be DC coupled with external circuitry. Vertical dynamic focus is combined with horizontal one on output pin 10. Dynamic horizontal phase control current drives internally the H-position, moving the Hfly position on the horizontal sawtooth in the 1.4% Th both on side pin balance and parallelogrm.
30
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
EW EWOUT = 2.5V + K1 ( VOUT - VDCMID )2 + K2 ( VOUT - VDCMID ) K1 is adjustable by EW amplitude I2C register K2 is adjustable by keystone I2C register Dynamic horizontal phase control IOUT = K3 ( VOUT - VDCMID ) 2 + K4 ( VOUT - VDCMID ) K4 is adjustable by side pin balance I2C register K3 is adjustable by parallelogram I2C register. Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. Typical free running frequency can be calculated by: 1 f0 (Hz)= 1.5*10-5 * C
OSC
A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can synchronise the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on pin 22. A capacitor in the range [150nF, 220nF] 5% is recommanded for application in the following range: 50Hz to 165Hz. Typical maximum and minimum frequency, at 25C and without any correction (S correction or C correction), can be calculated by: f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0 If S or C corrections are applied, these values are slighty affected. If a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin 22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Good stability of the internal closed loop is reached by a 470nF 5% capacitor value on pin 20 (VAGC)
31
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
CHARGE CURRENT
TRANSCONDUCTANCE AMPLIFIER REF
22 DISCH. +
SAMPLING 20 SAMP CAP
S CORRECTION
VS_AMP SUB07/8bits COR-C SUB08/6bits
OSC CAP
2
V-SYNC
SYNCHRO POLARITY
OSCILLATOR
C CORRECTION
+
-
Vlow
Switch Dlech
23 VOUT 18 BREATH
VERT_AMP SUB05/7BITS VMOIRE SUB0C/5BITS VOSITION SUB06/7BITS
Figure 18. AGC Loop Block Diagram I2C Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally. Their amplitude are adjustable by their respective I2C register. They can also be inhibited by their select bit. Endly, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 * VREF 300mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the non-inverting input of booster should also derive from VREF-V to optimize the accuracy(see Application Diagram). Basic Equations In first approximation, the amplitude of the ramp on pin 23 (Vout) is: VOUT - VPOS = ( VOSC - VDCMID ) * ( 1 + 0.25 (VAMP) ) with: - VDCMID = 7/16*VREF( typically 3.5V, the middle value of the ramp on pin 22) - VOSC = V22 ( ramp with fixed amplitude) - VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum - VPOS is calculated by : VPOS = VDCMID + 0.3Vp with Vp equals -1 for minimum vertical position register value and +1 for maximum The current available on Pin 22 is : IOSC = 3 8 * VREF * COSC * f
32
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
S1D2511B01
with COSC: capacitor connected on pin 22 f: synchronisation frequency. Vertical Moire By using the vertical moire, VPOS can be modulated from to frame. This function is intended to cancel the fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude pf the modulation is controlled by register VMOIRE on sub-off via the control bit D7. DC/DC CONVERTER PART This unit controls the switch-mode DC/DC con-verter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency)necessary for the horizontal scanning. This DC/DC converter can be configured either in step-up or step-down mode. In both cases it oper-ates very similarly to the well known UC3842. Step-up Mode Operating Description - The powerMOSisswitched-onduringthe flyback (at the beginning of the positive slope of the horizontal focus sawtooth). - The power MOS is switched-off when its current reachesa predeterminedvalue. Forthispurpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). - The feedback(coming either from the EHV or from the flyback) is divided to a voltage close to 4.8V and compared pared to the internal 4.8V reference(IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current. Main Features - Switching synchronized on the horizontal fre-quency, - B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis. Step-down Mode In step-down mode, the Isense information is not used any more and therefore not sent to the Pin16. This mode is selected by connecting this Pin16 to a DC voltage higher than 6V (for example VREF-V). Operating Description - The powerMOSis switched-onas for thestep-up mode. - The feedbackto the error amplifier is done as for the step-up mode. - The power MOS is switched-off when the HFOCUSCAP voltage get higher than the error amplifier output voltage
Main Features - Switching synchronized on the horizontal fre-quency, - B+ voltage always lower than the DC source, - No current limitation.
33
S1D2511B01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
APPLICATION CIRCUIT
VCC=12V
HSYNC
1K
5V 1 HSYNC_IN 5V 32 + 100uF 31 100 30 100 0.1uF
VSYNC
1K
2
VSYNC_IN
SDA
SDA
3
H_LOCKOUT
SCL
SCL
22nF 100V 4 1% P 820pF 50V 5
PLL2C
VCC
29 + 100uF 28 0.1uF 10K
CO
B+OUT
6.8K
6
RO
GND
27 1K
4.7uF 50V 1.8K 10nF 100V MP 1uF
7
PLL1F
H_OUT
26 22K
HOUT
+
8 820pF 9 10K 10 11 AFC 12 AFC 4.7uF 0.1uF 14 1M 22K 50K 22K 50K 3.3K 33K 15 13
HPOSITION
XRAY
25
50K
S1D2511B KB2511B
HFOCUSCAP EWOUT 24 10K
H_FOCUS
VOUT
23
10K
HGND
VSCAP
22
150nF 100V 1% P
HFLY
V_REF
21 +47uF 50V 0.1uF
H_REF
VAGCCAP
20 470nF 63V P
+
16
COMP
VGND
19
10K
1K
50K REGIN BREATH 18 1K I_SENSE B+GND 17
12V SCLK 1 SDAT 2 1 ACK 3 2 4 3 4 5 6 7 12 11 10 9 8 SCL SDA + 0.1uF 100uF 6 7 8 11 10 9 10K 33pF AFC HOUT 4 5 13 13
74HCT125
5V 14 100K
47pF
1 2 3
16 15 47pF 14 100K
MC14528
12
34

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